Microdevices, such as integrated microcircuits and microelectromechanical systems (MEMS), are used in a variety of products, from automobiles to microwaves to personal computers. Designing and fabricating microdevices typically involves many steps, known as a “design flow.” The particular steps of a design flow often are dependent upon the type of microcircuit, its complexity, the design team, and the microdevice fabricator or foundry that will manufacture the microcircuit. Typically, software and hardware “tools” verify the design at various stages of the design flow by running software simulators and/or hardware emulators, and errors in the design are corrected or the design is otherwise improved.
Several steps are common to most design flows for integrated microcircuits. Initially, the specification for a new circuit is transformed into a logical design, sometimes referred to as a register transfer level (RTL) description of the circuit. With this logical design, the circuit can be described in terms of both the exchange of signals between hardware registers and the logical operations that can be performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as the Very high speed integrated circuit Hardware Design Language (VHDL). As part of the creation of a logical design, a designer will also implement a place-and-route process to determine the placement of the various portions of the circuit, along with an initial routing of interconnections between those portions. The logic of the circuit is then analyzed, to confirm that it will accurately perform the functions desired for the circuit. This analysis is sometimes referred to as “functional verification.”
After the accuracy of the logical design is confirmed, it is converted into a device design by synthesis software. The device design, which is typically in the form of a schematic or netlist, describes the specific electronic devices, such as transistors, resistors, and capacitors, which will be used in the circuit, along with their interconnections. This device design generally corresponds to the level of representation displayed in conventional circuit diagrams. Preliminary timing estimates for portions of the circuit may be made at this stage, using an assumed characteristic speed for each device. In addition, the relationships between the electronic devices are analyzed, to confirm that the circuit described by the device design will correctly perform the desired functions. This analysis is sometimes referred to as “formal verification.”
Once the relationships between circuit devices have been established, the design can be again transformed, this time into a physical design that describes specific geometric elements. This type of design often is referred to as a “layout” design. The geometric elements, which typically are polygons, define the shapes that will be created in various materials to manufacture the circuit. Typically, a designer will select groups of geometric elements representing circuit device components, e.g., contacts, gates, etc., and place them in a design area. These groups of geometric elements may be custom designed, selected from a library of previously-created designs, or some combination of both. Once the groups of geometric elements representing circuit device components have been placed, geometric elements representing connection lines then are then placed between these geometric elements according to the predetermined route. These lines will form the wiring used to interconnect the electronic devices.
Typically, a designer will perform a number of analyses on the resulting layout design data. For example, with integrated circuits, the layout design may be analyzed to confirm that it accurately represents the circuit devices and their relationships as described in the device design. The layout design also may be analyzed to confirm that it complies with various design requirements, such as minimum spacings between geometric elements. Still further, the layout design may be modified to include the use of redundant geometric elements or the addition of corrective features to various geometric elements, to counteract limitations in the manufacturing process, etc. For example, the design flow process may include one or more resolution enhancement technique (RET) processes, that modify the layout design data to improve the usable resolution of the reticle or mask created from the design in a photolithographic manufacturing process.
After the layout design has been finalized, it is converted into a format that can be employed by a mask or reticle writing tool to create a mask or reticle for use in a photolithographic manufacturing process. The written masks or reticles then can be used in a photolithographic process to expose selected areas of a wafer to light or other radiation in order to produce the desired integrated microdevice structures on the wafer.
Returning to “functional verification,” this type of analysis begins with a circuit design coded at a register transfer level (RTL), which can be simulated and/or emulated by a design verification tool. The design verification tool can generate test stimulus that, when provided to the circuit design, can exercise the functionality of the circuit design. To inspect the operation of the circuit design in response to the test stimulus, verification engineers often employ Verification Intellectual Property (VIP) blocks written in a verification language, such as SystemVerilog or Universal Verification Methodolgy (UVM), which can run in a hardware modeling language along with the circuit design. During operation of the circuit design, these VIP blocks can monitor signals in the circuit design and perform on-the-fly checks of those signals.
While VIP blocks can check functional operation of the circuit design running in the hardware modeling language, as functionality becomes more complex, such as functionality of distributed state machines in the circuit design, communication protocols implemented in the circuit design, or the like, the VIP blocks can become large pieces of code that consume a non-trivial portion of processing resources or hardware capacity of a system implementing the hardware modeling language. As a result, many verification engineers limit their utilization of VIP blocks to check whether single instances of a state machine or communication protocol is following the specification. For example, the VIP blocks can check that a processor issues a snoop message when a particular type of transaction occurred, but do not attempt to track progress of that snoop message through the circuit design to see that another processor or snoop filter reacted correctly to the snoop message. In another example, for any distributed state machine, such as a coherent cache, the VIP blocks typically check that one piece of the state machine works, but will not verify the functionality of the entire state machine. In other words, while VIP blocks can allow the system implementing the hardware modeling language to perform check simple functionality, attempts to utilize VIP blocks to perform larger checks of sub-systems, protocols, and state machines of the circuit design comes with performance and resource tradeoffs that render their use impractical.